Digital signal processors and/or co-processors are typically utilized to perform computationally intensive data processing in a wide variety of wireless communication systems. In digital signal processing, correlation (also known as cross-correlation, sliding dot product or inner-product) is a measure of similarity between an input waveform signal and a reference waveform signal as a function of an applied time lag.
A correlator typically receives and compares a sequence of input signals along with its one or more shifted versions with a sequence of reference signal and produces a profile, one value for each original and shifted version (each time lag), in order to determine one or more appropriate shifted versions most resembling the reference sequence. Such correlation computation can be extensively utilized in the communication systems to determine the timing of a pre-determined ‘pilot’ signal as well as in applications such as pattern recognition, single particle analysis, electron tomographic averaging, and cryptanalysis. For an input sequence length of L and a number of time lags W, the required computation complexity is O(L*W). Because of the large number of calculations required, it is therefore highly desirable to accelerate correlation computation in such wireless communication applications.
However, adding an instruction (intrinsic) to accelerate the correlation in traditional digital signal processors, which have very limited number of operands and memory accesses per instruction, is difficult because of the large number of input data required in the correlation for high speedup. The large number of input data translates to memory width increase and therefore memory bandwidth increase in a traditional digital signal processor. More recent digital vector processors/co-processors offers a wider data path and can have more operands than traditional digital signal processors. The number of input data required, however, is still too large for very fast applications.
Most prior art approaches for accelerating correlation computation include a software application that is implemented in association with the digital signal processor and/or co-processor of the wireless communication system. Furthermore, a hard-wired accelerator can be configured in association with the digital signal processor in order to handle correlation computation in receiver functions such as a path searcher in a wideband code division multiple access (WCDMA) RAKE receiver. The operations of the accelerator typically include setting up parameters, shipping the data out of processor to the accelerator, and reading the result from the processor. Such prior art approaches, however, incur long latency and lack flexibility, thus hindering the ability of digital signal processors to support the evolving wireless communication standards.
Based on the foregoing, it is believed that a need exists for an improved method and system for providing an easily programmable, flexible and memory bandwidth efficient correlation accelerated instruction in the context of digital signal processors and/or coprocessors, as described in greater detail herein.